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LFEC3 Datasheet(PDF) 63 Page - Lattice Semiconductor |
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LFEC3 Datasheet(HTML) 63 Page - Lattice Semiconductor |
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63 / 163 page  3-27 DC and Switching Characteristics Lattice Semiconductor LatticeECP/EC Family Data Sheet Figure 3-14. sysCONFIG Master Serial Port Timing Figure 3-15. sysCONFIG Slave Serial Port Timing Figure 3-16. Power-On-Reset (POR) Timing CCLK (output) DIN DOUT t SUMCDI t HMCDI t CODO CCLK (input) DIN DOUT t SUSCDI t HSCDI t CODO t SSCL t SSCH CCLK 2 DONE VCC/VCCAUX 1 CFG[2:0] 3 t ICFG Valid INITN t VMC t SUCFG t HCFG 1. Time taken from VCC or VCCAUX, whichever is the last to reach its VMIN. 2. Device is in a Master Mode. 3. The CFG pins are normally static (hard wired). |
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Similar Description - LFEC3 |
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