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ISPLSI2128VE135LT100 Datasheet(PDF) 11 Page - Lattice Semiconductor |
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ISPLSI2128VE135LT100 Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 20 page Specifications ispLSI 2128VE 11 Signal Descriptions RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in the device. BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. TCK/IN 3 Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TMS/IN 1 Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TDO/IN 2 Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. IN 4 - IN 7 Dedicated Input Pins to the device. GND Ground (GND) VCC Vcc NC1 No Connect I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array. Signal Name Description 1. NC pins are not to be connected to any active signals, VCC or GND. |
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