ISPPAC-POWR60401TNE datasheet(3/29 Pages) LATTICE

Part #	ISPPAC-POWR60401TNE

Description	In-System Programmable Power Supply Sequencing Controller and Monitor

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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Lattice Semiconductor

ispPAC-POWR604 Data Sheet

2-3

Pin Descriptions

Number

Name

Pin Type

Voltage Range

Description

1

NC

—

No Connect

2

NC

—

No Connect

3

NC

—

No Connect

4

NC

—

No Connect

5

VDD

Power

2.25V-5.5V

Main Power Supply

6

IN1

CMOS Input

VDDINP

1, 3

Input 1

7

IN2

CMOS Input

VDDINP

1, 3

Input 2

8

IN3

CMOS Input

VDDINP

1, 3

Input 3

9

IN4

CMOS Input

VDDINP

1, 3

Input 4

10

RESET

CMOS input

VDD

6

PLD Reset Input, Active Low

11

VDDINP

Power

2.25V-5.5V

3

Digital Inputs Power Supply

12

OUT5

8

O/D Output

2.25V-5.5V

2

Open-Drain Output

13

OUT6

8

O/D Output

2.25V-5.5V

2

Open-Drain Output

14

OUT7

8

O/D Output

2.25V-5.5V

2

Open-Drain Output

15

OUT8

8

O/D Output

2.25V-5.5V

2

Open-Drain Output

16

NC

—

No Connect

17

NC

—

No Connect

18

COMP6

O/D Output

2.25V-5.5V

2

VMON6 Comparator Output (Open-Drain)

19

COMP5

O/D Output

2.25V-5.5V

2

VMON5 Comparator Output (Open-Drain)

20

COMP4

O/D Output

2.25V-5.5V

2

VMON4 Comparator Output (Open-Drain)

21

COMP3

O/D Output

2.25V-5.5V

2

VMON3 Comparator Output (Open-Drain)

22

COMP2

O/D Output

2.25V-5.5V

2

VMON2 Comparator Output (Open-Drain)

23

COMP1

O/D Output

2.25V-5.5V

2

VMON1 Comparator Output (Open-Drain)

24

TCK

TTL/LVCMOS Input

VDD

Test Clock (JTAG Pin)

25

POR

O/D Output

2.25V-5.5V

Power-On-Reset Output

26

CLK

Bi-directional I/O

VDD

2, 5

Clock Output (Open-Drain) or Clock Input

27

GND

Ground

28

TDO

TTL/LVCMOS Output

VDD

Test Data Out (JTAG Pin)

29

TRST

TTL/LVCMOS Input

VDD

Test Reset, Active Low, 50k Ohm Internal Pull-up

(JTAG Pin, Optional Use)

30

TDI

TTL/LVCMOS Input

VDD

Test Data In, 50k Ohm Pull-up (JTAG Pin)

31

TMS

TTL/LVCMOS Input

VDD

Test Mode Select, 50k Ohm Internal Pull-up (JTAG

Pin)

32

VMON1

Analog Input

0V-5.72V

4

Voltage Monitor Input 1

33

VMON2

Analog Input

0V-5.72V

4

Voltage Monitor Input 2

34

VMON3

Analog Input

0V-5.72V

4

Voltage Monitor Input 3

35

VMON4

Analog Input

0V-5.72V

4

Voltage Monitor Input 4

36

VMON5

Analog Input

0V-5.72V

4

Voltage Monitor Input 5

37

VMON6

Analog Input

0V-5.72V

4

Voltage Monitor Input 6

38

NC

—

No Connect

39

CREF

Reference

1.17V

7

Reference for Internal Use, Decoupling Capacitor

(.1uf Required, CREF to GND)

40

NC

—

No Connect

41

NC

—

No Connect

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ISPPAC-POWR60401TNE Datasheet(PDF) 3 Page - Lattice Semiconductor

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