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ISPLSI2032VE110LT48 Datasheet(PDF) 6 Page - Lattice Semiconductor |
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ISPLSI2032VE110LT48 Datasheet(HTML) 6 Page - Lattice Semiconductor |
6 / 15 page Specifications ispLSI 2032VE 6 External Timing Parameters Over Recommended Operating Conditions tpd1 UNITS -135 MIN. TEST COND. 1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030B/2032VE v.0.1 1 3 2 1 tsu2 + tco1 ( ) -110 MIN. MAX. MAX. DESCRIPTION # PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns tpd2 A 2 Data Propagation Delay – – ns fmax A 3 Clock Frequency with Internal Feedback 135 – 111 – MHz fmax (Ext.) – 4 Clock Frequency with External Feedback – – MHz fmax (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clock 5.5 – ns tco2 A 10 GLB Reg. Clock to Output Delay – – ns th2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass – – ns trw1 – 13 Ext. Reset Pulse Duration 5.0 – ns tptoeen B 14 Input to Output Enable – – ns tptoedis C 15 Input to Output Disable – – ns tgoeen B 16 Global OE Output Enable – – ns tgoedis C 17 Global OE Output Disable – – ns twh – 18 External Synchronous Clock Pulse Duration, High 3.0 – – ns twl – 19 External Synchronous Clock Pulse Duration, Low 3.0 – – ns 100 167 4.0 4.5 – – 5.5 – 9.0 – 12.0 12.0 6.0 6.0 10.0 77.0 125 5.5 0.0 7.5 0.0 6.5 4.0 4.0 13.0 5.0 6.5 12.5 14.5 14.5 7.0 7.0 -180 MIN. MAX. – 5.0 – 180 – – – – – – – – – – – – – – – – – 118 200 3.0 0.0 4.0 0.0 4.0 2.5 2.5 7.5 4.0 5.0 6.0 10.0 10.0 5.0 5.0 |
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