In-System Programmable High Density PLD

1016e_09

1

Lead-

Free

Package

Options

Available!

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

—

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

Functional Block Diagram

CLK

A0

A1

A2

A3

A4

A5

A6

A7

B

7

B

6

B

5

B

4

B

3

B

2

B

1

B

0

Global Routing Pool (GRP)

Logic

Array

DQ

DQ

DQ

DQ

GLB

0139C1-isp

Description

The ispLSI 1016E is a High Density Programmable Logic

Device containing 96 Registers, 32 Universal I/O pins,

four Dedicated Input pins, three Dedicated Clock Input

pins, one Global OE input pin and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1016E offers

5V non-volatile in-system programmability of the logic, as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1016

architecture, the ispLSI 1016E device adds a new global

output enable pin.

The basic unit of logic on the ispLSI 1016E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1...B7 (see Figure 1). There are a total of 16 GLBs in the

ispLSI 1016E device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinatorial

or registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006