Specifications ispLSI 1048E

9

1. Internal timing parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

Table 2-0037A/1048E

Outputs

UNITS

-100

MIN.

-90

MIN.

MAX.

MAX.

DESCRIPTION

#

PARAMETER

49 Output Buffer Delay

–

–

1.7

ns

51 I/O Cell OE to Output Enabled

–

–

6.4

ns

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

2.0

2.8

2.8

ns

Global Reset

2.0

5.1

Clocks

2.0

59 Global Reset to GLB and I/O Registers

–

–

4.5

ns

4.3

52 I/O Cell OE to Output Disabled

–

–

6.4

ns

5.1

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.0

2.8

2.8

ns

2.0

56 Clock Delay, Clock GLB to Global GLB Clock Line

0.8

0.8

1.8

ns

1.8

57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

0.0

0.0

0.5

ns

0.0

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

0.8

0.8

1.8

ns

1.8

53 Global OE

–

–

2.6

ns

3.9

50 Output Slew Limited Delay Adder

–

–

12.0

ns

10.0

-125

MIN. MAX.

–

–

0.9

1.3

4.3

0.9

–

2.8

–

4.3

0.9

0.9

0.8

1.8

0.0

0.0

0.8

1.8

–

2.7

–

10.0