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ISPPACCLK5320S-01TN64I Datasheet(PDF) 9 Page - Lattice Semiconductor |
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ISPPACCLK5320S-01TN64I Datasheet(HTML) 9 Page - Lattice Semiconductor |
9 / 56 page Lattice Semiconductor ispClock5300S Family Data Sheet 9 Output Rise and Fall Times – Typical Values 1, 2 Output Test Loads Figures 6 and 7 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 6. CMOS Termination Load Figure 7. eHSTL/HSTL/SSTL Termination Load Output Type Slew 1 (Fastest) Slew 2 Slew 3 Slew 4 (Slowest) Units tR tF tR tF tR tF tR tF LVTTL 0.54 0.76 0.60 0.87 0.78 1.26 1.05 1.88 ns LVCMOS 1.8V 0.75 0.69 0.88 0.78 0.83 1.11 1.20 1.68 ns LVCMOS 2.5V 0.57 0.69 0.65 0.78 0.99 0.98 1.65 1.51 ns LVCMOS 3.3V 0.55 0.77 0.60 0.87 0.78 1.26 1.05 1.88 ns SSTL18 0.55 0.40 —————— ns SSTL2 0.50 0.40 —————— ns SSTL3 0.50 0.45 —————— ns HSTL 0.60 0.45 —————— ns eHSTL 0.55 0.40 —————— ns 1. See Figures 6 and 7 for test conditions. 2. Measured between 20% and 80% points. ispClock SCOPE 950Ω 50Ω/3" 50Ω/36" 50Ω 5pF Zo = 50Ω ispCLOCK SCOPE 50Ω/3" 50Ω/36" 950Ω 50Ω 5pF Zo = HSTL: ~20Ω SSTL: 40Ω VTERM 50Ω |
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