ISPLSI1048E90LQI datasheet(11/17 Pages) LATTICE

Part #	ISPLSI1048E90LQI

Description	In-System Programmable High Density PLD

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Manufacturer	LATTICE [Lattice Semiconductor]

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Specifications ispLSI 1048E

11

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

0491

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control

PTs

Input

Register

Clock

Distribution

I/O Pin

(Input)

Y0

Y1,2,3

D

Q

GRP4

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#23 - 27

#30

#35

#34

Comb 4 PT Bypass

#36 - 38

#55 - 58

#44 - 46

#54

#53

#47

#48

Reset

Ded. In

GOE 0,1

#28

#22

RST

#59

#39

#40 - 43

#51, 52

#49, 50

GRP Loading

Delay

#29, 31-33

Derivations of

tsu, th and tco from the Product Term Clock1

=

tsu

2.2 ns

Logic + Reg su - Clock (min)

(

tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))

(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)

(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)

=

th

Clock (max) + Reg h - Logic

(

tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)

(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)

=

tco

Clock (max) + Reg co + Output

(

tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

(#22 + #30 + #46) + (#42) + (#47 + #49)

(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)

Table 2-0042/1048E

Derivations of

tsu, th and tco from the Clock GLB 1

=

tsu

Logic + Reg su - Clock (min)

(

tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))

(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)

(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)

=

th

Clock (max) + Reg h - Logic

(

tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)

(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)

=

tco

Clock (max) + Reg co + Output

(

tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

(#54 + #42 + #56) + (#42) + (#47 + #49)

(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)

3.5 ns

10.9 ns

3.4 ns

2.2 ns

9.6 ns

1. Calculations are based upon timing specifications for the ispLSI 1048E-125.

ispLSI 1048E Timing Model

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