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ISPPACCLK5610AV-01TN100I Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPPACCLK5610AV-01TN100I Datasheet(HTML) 2 Page - Lattice Semiconductor |
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2 / 51 page  Lattice Semiconductor ispClock5600A Family Data Sheet 1-2 General Description and Overview The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen- erators designed for use in high performance communications and computing applications. The ispClock5610A provides up to 10 single-ended or five differential clock outputs, while the ispClock5620A provides up to 20 single- ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent programmable control of termination, slew-rate, and timing skew. All configuration informa- tion is stored on-chip in non-volatile E 2CMOS memory. The ispClock5600A’s PLL and divider systems supports the synthesis of multiple clock frequencies derived from the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V- dividers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feed- back may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/- pins. The core functions of all members of the ispClock5600A family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5610A and ispClock5620A. Table 1-1. ispClock5600A Family Members Figure 1-1. ispClock5610A Functional Block Diagram Device Ref. Input Pairs Feedback Input Pairs Clock Outputs ispClock5610A 1 1 10 ispClock5620A 2 2 20 VCO LOOP FILTER PHASE DETECT LOCK DETECT M N INPUT DIVIDER FEEDBACK SKEW ADJUST 1 0 FEEDBACK DIVIDER GOE OEX LOCK PLL_BYPASS JTAG INTERFACE OEY TDI TMS TCK TDO SGATE SKEW CONTROL OUTPUT DRIVERS BANK_3 BANK_3 BANK_4 BANK_4 OUTPUT DIVIDERS OUTPUT ROUTING MATRIX RESET V1 V2 V0 V3 V4 BANK_0 BANK_0 BANK_1 BANK_1 BANK_2 BANK_2 PS0 PS1 Profile Select Control 01 2 3 OUTPUT ENABLE CONTROLS (1-40) (1-40) (2-80) (2-80) (2-80) (2-80) (2-80) REFA+ REFA- REFVTT FBKA+ FBKA - FBKVTT E 2 Configuration |
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