ISPPACCLK5610AV-01T100I datasheet(8/51 Pages) LATTICE

Part #	ISPPACCLK5610AV-01T100I

Description	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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Lattice Semiconductor

ispClock5600A Family Data Sheet

1-8

Switching Characteristics – Timing Adders for I/O Modes

Adder Type

Description

Min.

Typ.

Max.

Units

tIOI Input Adders

2

LVTTL_in

Using LVTTL Standard

0

ps

LVCMOS18_in

Using LVCMOS 1.8V Standard

-99

80

315

ps

LVCMOS25_in

Using LVCMOS 2.5V Standard

0

ps

LVCMOS33_in

Using LVCMOS 3.3V Standard

0

ps

SSTL18_in

Using SSTL18 Standard

10

360

642

ps

SSTL2_in

Using SSTL2 Standard

64

420

679

ps

SSTL3_in

Using SSTL3 Standard

34

380

630

ps

HSTL_in

Using HSTL Standard

231

672

1064

ps

eHSTL_in

Using eHSTL Standard

128

514

846

ps

LVDS_in

Using LVDS Standard

118

426

651

ps

LVPECL_in

Using LVPECL Standard

201

593

937

ps

tIOO Output Adders

1, 3

LVTTL_out

Output Conﬁgured as LVTTL Buffer

116

395

553

ps

LVCMOS18_out

Output Conﬁgured as LVCMOS 1.8V Buffer

155

510

730

ps

LVCMOS25_out

Output Conﬁgured as LVCMOS 2.5V Buffer

124

387

592

ps

LVCMOS33_out

Output Conﬁgured as LVCMOS 3.3V Buffer

116

395

553

ps

SSTL2_out

Output Conﬁgured as SSTL2 Buffer

-109

66

209

ps

SSTL3_out

Output Conﬁgured as SSTL3 Buffer

-97

78

242

ps

SSTL18_out_diff

Output Conﬁgured as SSTL18 Buffer (Differential)

-153

41

228

ps

HSTL_out_diff

Output Conﬁgured as HSTL Buffer (Differential)

-4

180

402

ps

eHSTL_out_diff

Output Conﬁgured as eHSTL Buffer (Differential)

-16

173

375

ps

SSTL_out_diff

Output Conﬁgured as SSTL2 Buffer (Differential)

-146

83

305

ps

LVDS_out

Output Conﬁgured as LVDS Buffer

0

ps

LVPECL_out

Output Conﬁgured as LVPECL Buffer

-187

-17

57

ps

tIOS Output Slew Rate Adders

1

Slew_1

Output Slew_1 (Fastest)

—

0

—

ps

Slew_2

Output Slew_2

—

330

—

ps

Slew_3

Output Slew_3

—

660

—

ps

Slew_4

Output Slew_4 (Slowest)

—

1320

—

ps

1. Measured under standard output load conditions. See Figures 1-3-1-5.

2. All input adders referenced to LVCMOS33.

3. All output adders referenced to LVDS.

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ISPPACCLK5610AV-01T100I Datasheet(PDF) 8 Page - Lattice Semiconductor

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