Lattice Semiconductor

ispClock5500 Family Data Sheet

10

Performance Characteristics – PLL

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

Reference input frequency

range

10

—

320

MHz

Reference input clock HIGH and

LOW times

1.25

—

—

ns

Input rise and fall times

Measured between 20% and 80%

levels

——

5

ns

M-divider range

1

—

32

N-Divider range

1

—

32

Phase detector input frequency

range

2

10

—

320

MHz

VCO operating frequency

320

—

640

MHz

Output Divider range

Even integer values only

2

—

64

Output frequency range

1

Fine Skew Mode,

10

—

320

MHz

Coarse Skew Mode,

5

—

160

MHz

Output adjacent-cycle jitter

1000 cycle sample

3

—

55

70

ps (p-p)

Output period jitter

10000 cycle sample

3

—

11

14

ps (RMS)

Reference clock to output jitter

6000 cycle sample

3

—

170

—

ps (RMS)

tφ

Static phase offset

PFD input frequency ≥ 100MHz

5

—

-500

—

ps

Output duty cycle error (see

Table 3 for nominal values)

4

6

—

—

260

ps

Output type LVCMOS 3.3V

6

—

—

300

ps

Reference clock to output delay,

PLL bypass mode

Inputs and Outputs configured to

LVCMOS 3.3V standard

—5—

ns

PLL Lock time

From Power-up event

—

150

500

µs

From Reset event

—

15

50

µs

PSR

Power supply rejection, period

jitter vs. power supply noise

VCCA = VCCD = VCCO modulated

with 100kHz sinusoidal stimulus

—

0.05

—

1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).

2. Dividers should be set so that they provide the phase detector with signals of 10MHz or greater for loop stability.

5. Input and outputs LVPECL mode.

6. See Figures 3-5 for output loads.

ps(RMS)

mV(p-p)