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ISPCLOCK5500 Datasheet(PDF) 11 Page - Lattice Semiconductor |
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ISPCLOCK5500 Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 48 page Lattice Semiconductor ispClock5500 Family Data Sheet 11 Timing Specifications Skew Matching Programmable Skew Control Control Functions Figure 6. RESET and Profile Select Timing Symbol Parameter Conditions Min. Typ. Max. Units tSKEW Output-output Skew Between any two identically configured and loaded outputs regardless of bank. — — 50 ps Symbol Parameter Conditions Min. Typ. Max. Units tSKRANGE Skew Control Range 1 Fine Skew Mode, fVCO = 320 MHz — 5.86 — ns Fine Skew Mode, fVCO = 640 MHz — 2.93 — Coarse Skew Mode, fVCO = 320 MHz — 11.72 — Coarse Skew Mode, fVCO = 640 MHz — 5.86 — SKSTEPS Skew Steps per range — 16 — tSKSTEP Skew Step Size 2 Fine Skew Mode, fVCO = 320 MHz — 390 — ps Fine Skew Mode, fVCO = 640 MHz — 195 — Coarse Skew Mode, fVCO = 320 MHz — 780 — Coarse Skew Mode, fVCO = 640 MHz — 390 — tSKERR Skew Time Accuracy 3 Fine skew mode — 30 — ps Coarse skew mode — 50 — 1. Skew control range is a function of VCO frequency (fVCO). In fine skew mode TSKRANGE = 15/(8 x fVCO). In coarse skew mode TSKRANGE = 15/(4 x fVCO). 2. Skew step size is a function of VCO frequency (fVCO). In fine skew mode TSKSTEP = 1/(8 x fVCO). In coarse skew mode TSKSTEP = 1/(4 x fVCO). 3. Only applicable to outputs with non-zero skew settings. Symbol Parameter Conditions Min. Typ. Max. Units tDIS/OE Delay Time, OEX or OEY to Output Disabled/ Enabled —10 20 ns tDIS/GOE Delay Time, GOE to Output Disabled/Enabled — 10 20 ns tSUSGATE Setup Time, SGATE to Output Clock Start/ Stop 3 — — cycles 1 tPLL_RSTW PLL Reset Pulse Width 15 — — µs tHPS_RST Hold time for RESET past change in PS[0..1] 20 — — ns 1. Output clock cycles for the particular output being controlled. tHPS_RST tPLL_RSTW PS[0..1] RESET |
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