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ISPCLOCK5300S Datasheet(PDF) 11 Page - Lattice Semiconductor |
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ISPCLOCK5300S Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 56 page Lattice Semiconductor ispClock5300S Family Data Sheet 11 Performance Characteristics – PLL Symbol Parameter Conditions Min. Typ. Max. Units fREF, fFBK Reference and feedback input frequency range 8 267 MHz tCLOCKHI, tCLOCKLO Reference and feedback input clock HIGH and LOW times 1.25 ns tRINP, tFINP Reference and feedback input rise and fall times Measured between 20% and 80% levels 5ns fPFD Phase detector input frequency range 8 267 MHz fVCO VCO operating frequency 160 400 MHz VDIV Output divider range (Power of 2) 132 fOUT Output frequency range 1 Fine Skew Mode 5 267 MHz Coarse Skew Mode 2.5 200 MHz tJIT (cc) Output adjacent-cycle jitter 5 (1000 cycle sample) fPFD ≥ 100MHz 70 ps (p-p) tJIT (per) Output period jitter 5 (10000 cycle sample) fPFD ≥ 100MHz 9 ps (RMS) tJIT(φ) Reference clock to output jitter 5 (2000 cycle sample) fPFD ≥ 100MHz 50 ps (RMS) tφ Static phase offset 4 PFD input frequency ≥100MHz 3 -40 100 ps tφDYN Dynamic phase offset 100MHz, Spread Spectrum Modulation index = 0.5% 28 ps DCERR Output duty cycle error Output type LVCMOS 3.3V 2 fOUT >100 MHz 47 53 % tPDBYPASS Reference clock to output propagation delay V=1 6.5 ns tPD_FOB Reference to output propagation delay in Non-Zero Delay Buffer Mode V=1 2.5 3.5 5 ns tDELAY Reference to output delay with internal feedback mode 3 V=1 500 ps tLOCK PLL lock time From Power-up event 150 µs From RESET event 15 µs tRELOCK PLL relock time To same reference frequency 15 µs To different frequency 150 µs PSR Power supply rejection, period jitter vs. power supply noise fIN = fOUT = 100MHz VCCA = VCCD = VCCO modulated with 100kHz sinusoidal stimulus 0.05 1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design). 2. See Figures 6 and 7 for output loads. 3. Input and outputs LVCMOS mode 4. Inserted feedback loop delay < 7ns 5. Measured with fOUT = 100MHz, fVCO = 400MHz, input and output interface set to LVCMOS. ps(RMS) mV(p-p) |
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