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STM703M6E Datasheet(PDF) 9 Page - STMicroelectronics |
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STM703M6E Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 37 page  9/37 STM690A/692A/703/704/802/805/817/818/819 OPERATION Reset Output The STM690A/692A/703/704/802/805/817/818/ 819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM805) for 0V < VCC < VRST if VBAT is greater than 1V. Without a back-up battery, RST is guar- anteed valid down to VCC =1V. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. Push-button Reset Input (STM703/704/819) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 42., page 28) after it returns high. The MR input has an internal 40k Ω pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open mo- mentary switch from MR to GND to create a man- ual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide ad- ditional noise immunity. MR may float, or be tied to VCC when not used. Watchdog Input (NOT available on STM703/ 704/819) The watchdog timer can be used to detect an out- of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec typ), the reset is asserted. The internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8sec (tWD + trec). The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is re- leased, the timer starts counting (see Figure 43., page 28). Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maxi- mum allowable leakage current is 10uA and the maximum allowable load capacitance is 200pF. Note: Input frequency greater than 20ns (50MHz) will be filtered. |
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