HCF40103BM1 datasheet(1/14 Pages) STMICROELECTRONICS

Part #	HCF40103BM1

Description	8-STAGE PRESETTABLE SYNCHRONOUS 8 BIT BINARY DOWN COUNTERS

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September 2002

s

SYNCHRONOUS OR ASYNCHRONOUS

PRESET

s

MEDIUM -SPEED OPERATION :

fCL =3.6MHz (Typ.) at VDD = 10V

s

CASCADABLE

s

QUIESCENT CURRENT SPECIF. UP TO 20V

s

5V, 10V AND 15V PARAMETRIC RATINGS

s

INPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C

s

100% TESTED FOR QUIESCENT CURRENT

s

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DESCRIPTION

HCF40103B is a monolithic integrated circuit

fabricated

in

Metal

Oxide

Semiconductor

technology available in DIP and SOP packages.

HCF40103B consists of an 8-stage synchronous

down counter with a single output that is active

when the internal count is zero. This device

contains a single 8-bit binary counter. It has

control inputs for enabling or disabling the clock,

for clearing the counter to its maximum count, and

for presetting the counter either synchronously or

asynchronously.

All

control

inputs

and

the

CARRY-OUT/ZERO

DETECT

output

are

active-low logics. In normal operation, the counter

is decremented by one count on each positive

transition of the CLOCK. Counting is inhibited

when the CARRY-IN/COUNTER ENABLE (CI/

CE) input is high. The CARRY-OUT/ZERO

DETECT (CO/ZD) output goes low when the

count reaches zero if the CI/CE input is low, and

remains low for one full clock period. When the

SYNCHRONOUS PRESET ENABLE (SPE) input

is low, data at the JAM input is clocked into the

counter on the next positive clock transition

regardless of the state of the CI/CE input. When

the ASYNCHRONOUS PRESET ENABLE (APE)

input

is

low,

data

at

the

JAM

inputs

is

asynchronously forced into the counter regardless

of the state of the SPE, CI/CE, or CLOCK inputs.

JAM inputs J0-J7 represent a single 8 bit binary

word. When the CLEAR (CLR) input is low, the

counter is asynchronously cleared to its maximum

count (25510) regardless of the state of any other

input. The precedent relationship between control

input is indicated in the truth table. If all control

HCF40103B

8-STAGE PRESETTABLE SYNCHRONOUS

8 BIT BINARY DOWN COUNTERS

PIN CONNECTION

ORDER CODES

PACKAGE

TUBE

T & R

DIP

HCF40103BEY

SOP

HCF40103BM1

HCF40103M013TR

DIP

SOP

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