Figure 14-13. Slave Command Sequence ............................................................................................ 343
Figure 15-1.
Ethernet Controller Block Diagram .................................................................................. 368
Figure 15-2.
Ethernet Controller ......................................................................................................... 368
Figure 15-3.
Ethernet Frame ............................................................................................................. 370
Figure 16-1.
Analog Comparator Module Block Diagram ..................................................................... 411
Figure 16-2.
Structure of Comparator Unit .......................................................................................... 412
Figure 16-3.
Comparator Internal Reference Structure ........................................................................ 413
Figure 17-1.
Pin Connection Diagram ................................................................................................ 423
Figure 20-1.
Load Conditions ............................................................................................................ 442
Figure 20-2.
I2C Timing ..................................................................................................................... 444
Figure 20-3.
External XTLP Oscillator Characteristics ......................................................................... 447
Figure 20-4.
Hibernation Module Timing ............................................................................................. 448
Figure 20-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 448
Figure 20-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 449
Figure 20-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 449
Figure 20-8.
JTAG Test Clock Input Timing ......................................................................................... 450
Figure 20-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 451
Figure 20-10. JTAG TRST Timing ........................................................................................................ 451
Figure 20-11. External Reset Timing (RST) .......................................................................................... 452
Figure 20-12. Power-On Reset Timing ................................................................................................. 452
Figure 20-13. Brown-Out Reset Timing ................................................................................................ 452
Figure 20-14. Software Reset Timing ................................................................................................... 453
Figure 20-15. Watchdog Reset Timing ................................................................................................. 453
Figure 21-1.
100-Pin LQFP Package .................................................................................................. 454
9
October 09, 2007
Preliminary
LM3S6611 Microcontroller