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74VHC132 Datasheet(PDF) 1 Page - STMicroelectronics |
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74VHC132 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 11 page 1/11 November 2004 s HIGH SPEED: tPD = 3.9 ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C s TYPICAL HYSTERESIS: Vh = 1V at VCC = 4.5V s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.8V (MAX.) DESCRIPTION The 74VHC132 is an advanced high-speed CMOS QUAD 2-INPUT SCHMITT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. Pin configuration and function are the same as those of the 74VHC00 but the 74VHC132 has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74VHC132 QUAD 2-INPUT SCHMITT NAND GATE Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74VHC132MTR TSSOP 74VHC132TTR TSSOP SOP Rev. 4 |
Similar Part No. - 74VHC132_04 |
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Similar Description - 74VHC132_04 |
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