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STLC5412P Datasheet(PDF) 7 Page - STMicroelectronics |
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STLC5412P Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 74 page  PIN FUNCTIONS (specific Micro Wire mode) Pin Name In/Out Description 12 BCLK In Out Bit clock input or output depending of the CMS bit in CMR register. When BCLK is an input, its frequency may be any multiple of 8 KHz from 256 KHz to 4096 KHz in formats 1, 2, 3; 512 KHz to 6176 KHz in format 4. When BCLK is an output, its frequency is 256 KHz, 512 KHz, 1536 KHz, 2048 KHz or 2560 KHz depending of the selection in CR1 register. In this case, BCLK is locked to the recovered clock received from the line. Input or Output BCLK is synchronous with FSa/FSb. Datas are shifted in and out (on Bx and Br) at the BCLK frequency in formats 1, 2, 3. In format 4 datas are shifted out at half the BCLK frequency. 13 Bx In 2B+D input. Basic access data to transmit to the line is shifted in on the falling edges (at the BCLK frequency or the half BCLK frequency if format 4 is selected) during the assigned time-slots. When D channel port is enabled, only B1 & B2 sampled on Bx. 14 DCLK Out D channel clock output when the D channel port is enabled in continuous mode. Datas are shifted in and out (on Dx and Dr) at 16 KHz on the falling and rising edges of DCLK respectively. In master mode, DCLK is synchronous with BCLK. 15 Dr Out D channel data output when the D channel port is enabled. D channel data is shifted out from the UID on this pin in 2 selectable modes: in TDM mode data is shifted out at the BCLK frequency (or half BCLK frequency in format 4) on the ridsing edges when the assigned time slot is active. In continuous mode data is shifted in at the DCLK frequency on the rising edge continuously. 16 Dx In D channel data input when the D channel port is enabled. D channel data is shifted in from the UID on this pin in 2 selectable modes: in TDM mode data is shifted in at the BCLK frequency (or half BCLK frequency in format 4) on the falling edges when the assigned time slot is active. In continuous mode data is shifted in at the DCLK frequency on the falling edge continuously. 17 CCLK In Clock input for the MICROWIRE control channel: data is shifted in and out on CI and CO pins with CCLK frequency following 2 modes. For each mode the CCLK polarity is indifferent. CCLK may be asynchronous with all the others UID clocks. 18 CI In MICROWIREcontrol channel serial input: Two bytes data is shifted in the UID on this pin on the rising or the falling edge of CCLK depending of the working mode. 19 CO Out MICROWIRE control channel serial output: two bytes data is shifted out the UID on this pin on the rising or the falling edge of CCLK depending of the working mode. When not enabled by CS low, CO is high impedance. 22 SFSx In Out Tx Super frame synchronization. The rising edge of SFSx indicates the beginning of the transmit superframe on the line. In NT mode SFSx is always an output. In LT mode SFSx is an input or an output depending of the SFS bit in CR2 register. When SFSx is input, it must be synchronous of FSa. In DECT mode this pin is always an input in LT configuration and is used to evaluate the round trip delay, in NT configuration is an output used to resynchronise the DECT frame counter.( refer to page 25) 25 SFSr Out Rx Super frame synchronization. The rising edge of SFSr indicates the beginning of the received superframe on the line. UID provides this output only when ESFR bit in CR4 register is set to 1. LSD Out Line Signal Detect output (default configuration): This pin is an open drain output which is normally in the high impedance state but pulls low when the device previously in the power down state receives a wake-up by Tone from the line. This signal is intended to be used to wake-up a micro-controller from a low power idle mode. The LSD output goes back in the high impedance state when the device is powered up. 26 INT Out Interrupt output: Latched open-drain output signal which is normally high impedance and goes low to request a read cycle. Pending interrupt data is shifted out from CO at the following read-write cycle. Several pending interrupts may be queued internally and may provide several interrupt requests. INT is freed upon receiving of CS low and can go low again when CS is freed. 27 CS In Chip Select input: When this pin is pulled low, data can be shifted in and out from the UID through CI & CO pins. When high, this pin inhibits the MICROWIRE interface. For normal read or write operation, CS has to be pulled low for 16 CCLK periods. STLC5412 7/74 |
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