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74ACT373M Datasheet(PDF) 1 Page - STMicroelectronics |
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74ACT373M Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page  1/11 April 2001 s HIGH SPEED: tPD = 6ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). When the (LE) input is high , the Q outputs follow the data (D) inputs . When the (LE) is taken low, the Q outputs will be latched at the logic levels set up at the D inputs. When the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); when the (OE) input is high, the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74ACT373B SOP 74ACT373M 74ACT373MTR TSSOP 74ACT373TTR TSSOP DIP SOP |
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