page 9 of 12

Digital Step Attenuator

DAT-15575-PN

DAT-15575-PN+

The parallel interface timing requirements are defined by Figure 1 (Parallel Interface Timing Diagram) and

Table 2 (Parallel Interface AC Characteristics), and switching speed.

For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenunation

state control values, then pulse LE HIGH to LOW (per Figure 1) to latch new attenuation state into device.

For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation

state control values will change device state to new attenuation. Direct mode is ideal for manual control of

the device (using hardwire, switches, or jumpers).

Simplified Schematic

Figure 1: Parallel Interface Timing Diagram

Table 1. Truth Table

Attenuation

State

C8

C4

C2

C1

C0.5

Reference

00000

0.5 (dB)

00001

1 (dB)

00010

2 (dB)

00100

4 (dB)

01000

8 (dB)

10000

15.5 (dB)

11111

Note: Not all 32 possible combinations of C0.5 - C8 are shown

in table

Table 2. Parallel Interface AC Characteristics

Symbol

Parameter

Min.

Max.

Units

t

LEPW

LE minimum pulse

width

30

ns

t

PDSUP

data set-up time before

clock rising edge of LE

10

ns

t

PDHLD

data hold time after

clock falling edge of LE

10

ns

The DAT-15575-PN parallel interface consists of 5 control bits that select the desired attenuation state, as

shown in Table 1: Truth Table

t

PDSUP

t

PDHLD

Parallel Data

C8:C0.5

LE

t

LEPW

RF Input

8dB

4dB

2dB

1dB

0.5dB

Parallel Control

Control Logic Interface

Latch Enable

RF Out