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STL35NF10 Datasheet(PDF) 1 Page - STMicroelectronics |
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STL35NF10 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 6 page 1/6 PRELIMINARY DATA August 2001 STL35NF10 N-CHANNEL 100V - 0.025 Ω - 35A PowerFLAT™ LOW GATE CHARGE STripFET™ MOSFET s TYPICAL RDS(on) = 0.025Ω s IMPROVED DIE-TO-FOOTPRINT RATIO s VERY LOW PROFILE PACKAGE DESCRIPTION This Power MOSFET is the second generation of STMicroelectronics unique “STripFET™” technolo- gy. The resulting transistor shows extremely low on- resistance and minimal gate charge. The new Pow- erFLAT™ package allows a significant reduction in board space without compromising performance. APPLICATIONS s HIGH EFFICIENCY ISOLATED DC/DC CONVETERS ABSOLUTE MAXIMUM RATINGS (q) Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STL35NF10 100 V < 0.030 Ω 35 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 100 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 100 V VGS Gate- source Voltage ± 20 V ID Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C 35 22 A A IDM (q) Drain Current (pulsed) 140 A PTOT Total Dissipation at TC = 25°C 80 W Derating Factor 0.64 W/°C EAS (1) Single Pulse Avalanche Energy 135 mJ Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature –55 to 150 °C (1) Starting Tj = 25°C, ID = 35A, VDD = 50V PowerFLAT™(6x5) (Chip Scale Package) INTERNAL SCHEMATIC DIAGRAM |
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