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L6452 Datasheet(PDF) 10 Page - STMicroelectronics |
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L6452 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 22 page Electrical specifications L6452 10/22 Tacqth Theoretical acquisition time fadck= 250 kHz 32.4 µs Tacqpr Real acquisition time fadck= 250 kHz 36 µs DIGITAL INTERFACE INPUT Vinp Schmitt Trigger positive-going Threshold 2/3Vdd V Vinm Schmitt Trigger negative-going Threshold 1/3Vdd V Vhys Schmitt Trigger Hysteresis 0.1 0.3 1 V Iin Input Current (Vin=0; Vdd=5) (4) 50 150 300 µA CR LATCH TIMINGS Tls Latch set up time 100 ns Tlhigh Latch high time 100 ns Tlconv Latch data valid to A/D input valid delay Selected channel: CH1..CH5 CH0 4 7 µs µs tstore Latching data time 200 ns Note: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the data 16 bit shift register (signals SDI, SDC) SHIFT REGISTER AND LATCH TIMING Ta Set up time 35 ns Tb Hold time 35 ns Tc Serial clock low time 35 ns Td Serial clock high time 35 ns Te Serial clock period 125 ns Tf Latch set up time 100 ns Tg Latch data high time 100 ns Tset NcEn setup time with respect to LongPulse (or ShortPulse) Asserted 160 ns Thold NcEn hold time with respect to LongPulse (or ShortPulse) Asserted 0ns Tlp Set-up time from latch to Pulse (short and long) 125 ns Tpl Time from Pulse deassertion to new data latching 125 ns Table 3. DC Electrical characteristics (Tj = 25°C) - continued Symbol Parameter Test Condition Min. Typ. Max. Unit |
Similar Part No. - L6452_06 |
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Similar Description - L6452_06 |
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