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MC54HC174A Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MC54HC174A
Description  Hex D Flip-Flop With Common Clock And Reset High-Performance Silicon-Gate CMOS
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC54HC174A Datasheet(HTML) 3 Page - Motorola, Inc

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MC54/74HC174A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v 125_C
v 85_C
– 55 to
25
_C
VCC
V
Test Conditions
Parameter
Symbol
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
4.0
40
160
µA
NOTES:
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola
High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + S∆ICC.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
– 55 to
25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPLH
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25
°C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Enabled Output)*
62
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Fig.
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Fig.
VCC
V
– 55 to 25
_C
v 85_C
v 125_C
Unit
Symbol
Parameter
Fig.
VCC
V
Min
Max
Min
Max
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
3
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Data
3
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
2
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
1
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tw
Minimum Pulse Width, Reset
2
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns


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