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V61C3181024 Datasheet(PDF) 8 Page - Mosel Vitelic, Corp

Part No. V61C3181024
Description  128K X 8 HIGH SPEED STATIC RAM
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Manufacturer  MOSEL [Mosel Vitelic, Corp]
Direct Link  http://www.moselvitelic.com
Logo MOSEL - Mosel Vitelic, Corp

V61C3181024 Datasheet(HTML) 8 Page - Mosel Vitelic, Corp

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V61C3181024 Rev. 1.3 February 1999
MOSEL VITELIC
V61C3181024
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
Write Cycle 2 (CE Controlled)(4)
NOTES:
1.
The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2.
tAH is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle.
3.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4.
OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5.
If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6.
tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
ADDRESS
OUTPUT
INPUT
CE1
CE2
WE
3181024 12
tWC
tCW
(6)
tCW
(6)
tDW
tDH
tAW
tAH
(2)
tWHZ
tWP
(1)
tAS
ADDRESS
OUTPUT
High-Z
INPUT
CE1
CE2
WE
3181024 13
tWC
tDW
tDH
tAW
tCW
(6)
tCW
(6)
tAH
(2)
tAS
(4)
(5)


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