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V61C3181024 Datasheet(PDF) 2 Page - Mosel Vitelic, Corp |
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V61C3181024 Datasheet(HTML) 2 Page - Mosel Vitelic, Corp |
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2 / 10 page  2 V61C3181024 Rev. 1.3 February 1999 MOSEL VITELIC V61C3181024 Pin Descriptions A0–A16 Address Inputs These 17 address inputs select one of the 128K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. WE Write Enable Input An active LOW input, WE input controls read and write operations. When CE and WE inputs are both LOW, the data present on the I/O pins will be written into the selected memory location. I/O0–I/O7 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. VCC Power Supply GND Ground Pin Configurations (Top View) 32-Pin SOJ 32-Pin TSOP-I 1 32 3181024 02 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND NC A11 CE2 WE A12 A13 A14 A15 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 3181024 03 A15 A14 A13 A12 A11 VCC NC A10 A9 A8 A7 A6 A5 A4 A16 CE2 WE I/O6 I/O7 I/O5 I/O4 I/O3 OE I/O1 I/O2 VSS CE1 I/O0 A0 A1 A2 A3 |
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