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V61C3181024 Datasheet(PDF) 1 Page - Mosel Vitelic, Corp |
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V61C3181024 Datasheet(HTML) 1 Page - Mosel Vitelic, Corp |
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1 / 10 page  MOSEL VITELIC 1 V61C3181024 128K X 8 HIGH SPEED STATIC RAM PRELIMINARY V61C3181024 Rev. 1.3 February 1999 Features s High-speed: 10, 12, 15 ns s Fully static operation s All inputs and outputs directly TTL compatible s Three state outputs s Low data retention current (VCC = 2V) s Single 3.3V ± 0.3 Power Supply s Low CMOS Standby current of 5 mA max s Packages – 32-pin TSOP – 32-pin 300 mil SOJ Description The V61C3181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The V61C3181024 is available in 32-pin SOJ and TSOP. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Temperature Mark T R 10 12 15 0 °C to 70°C ••••• Blank Functional Block Diagram Row Decoder Memory Array Input Data Circuit Column I/O Column Decoder Control Circuit VCC GND A0 3181024 01 A8 I/O0 I/O7 CE2 OE WE CE1 A9 A16 |
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