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C505_9708 Datasheet(PDF) 74 Page - Siemens Semiconductor Group |
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C505_9708 Datasheet(HTML) 74 Page - Siemens Semiconductor Group |
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74 / 227 page  On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-12 1997-08-01 6.1.4 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-8 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain reqirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. Figure 6-8 Port Timing MCT03231 P1 P2 S4 S5 P2 P1 S6 P2 P1 S1 P2 P1 S2 P2 P1 S3 P2 P1 XTAL2 Input sampled: e.g. MOV A, P1 Old Data New Data Port P1 active for 1 State (driver transistor) |
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