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C505_9708 Datasheet(PDF) 58 Page - Siemens Semiconductor Group

Part No. C505_9708
Description  8-Bit CMOS Microcontroller
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Manufacturer  SIEMENS [Siemens Semiconductor Group]
Direct Link  http://www.siemens.com/
Logo SIEMENS - Siemens Semiconductor Group

C505_9708 Datasheet(HTML) 58 Page - Siemens Semiconductor Group

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System Reset
C505 / C505C
Semiconductor Group
5-5
1997-08-01
5.3
Hardware Reset Timing
This section describes the timing of the hardware reset signal.
The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2.
Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found
active (high level) the internal reset procedure is started. It needs two complete machine cycles to
put the complete device to its correct reset state, i.e. all special function registers contain their
default values, the port latches contain 1's etc. Note that this reset procedure is also performed if
there is no clock available at the device. (This is done by the oscillator watchdog, which provides an
auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The
RESET signal must be active for at least one machine cycle; after this time the C505 remains in its
reset state as long as the signal is active. When the signal goes inactive this transition is recognized
in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output
(when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase
2) the first falling edge at pin ALE occurs.
Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus,
between the release of the RESET signal and the first falling edge at ALE there is a time period of
at least one machine cycle but less than two machine cycles.
Figure 5-3
CPU Timing after Reset
MCT02092
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
P1 P2
PCL
OUT
PCH
OUT
PCH
OUT
One Machine Cycle
RESET
P0
P2
ALE
Inst.
in
OUT
PCL


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