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LM3S628-IQN50 Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # LM3S628-IQN50
Description  Microcontroller
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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LM3S628 Data Sheet
October 8, 2006
5
Preliminary
10.5
Register Descriptions......................................................................................................................... 174
11.
Analog-to-Digital Converter (ADC) .................................................................................. 195
11.1
Block Diagram ................................................................................................................................... 195
11.2
Functional Description ....................................................................................................................... 196
11.2.1 Sample Sequencers .......................................................................................................................... 196
11.2.2 Module Control .................................................................................................................................. 197
11.2.3 Hardware Sample Averaging Circuit.................................................................................................. 197
11.2.4 Analog-to-Digital Converter ............................................................................................................... 197
11.2.5 Test Modes ........................................................................................................................................ 197
11.2.6 Internal Temperature Sensor ............................................................................................................. 198
11.3
Initialization and Configuration........................................................................................................... 198
11.3.1 Module Initialization ........................................................................................................................... 198
11.3.2 Sample Sequencer Configuration ...................................................................................................... 198
11.4
Register Map ..................................................................................................................................... 199
11.5
Register Descriptions......................................................................................................................... 200
12.
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 225
12.1
Block Diagram ................................................................................................................................... 226
12.2
Functional Description ....................................................................................................................... 226
12.2.1 Transmit/Receive Logic ..................................................................................................................... 226
12.2.2 Baud-Rate Generation ....................................................................................................................... 227
12.2.3 Data Transmission ............................................................................................................................. 228
12.2.4 FIFO Operation .................................................................................................................................. 228
12.2.5 Interrupts............................................................................................................................................ 228
12.2.6 Loopback Operation .......................................................................................................................... 229
12.3
Initialization and Configuration........................................................................................................... 229
12.4
Register Map ..................................................................................................................................... 230
12.5
Register Descriptions......................................................................................................................... 231
13.
Synchronous Serial Interface (SSI) ................................................................................. 261
13.1
Block Diagram ................................................................................................................................... 261
13.2
Functional Description ....................................................................................................................... 262
13.2.1 Bit Rate Generation ........................................................................................................................... 262
13.2.2 FIFO Operation .................................................................................................................................. 262
13.2.3 Interrupts............................................................................................................................................ 262
13.2.4 Frame Formats .................................................................................................................................. 263
13.3
Initialization and Configuration........................................................................................................... 270
13.4
Register Map ..................................................................................................................................... 271
13.5
Register Descriptions......................................................................................................................... 272
14.
Inter-Integrated Circuit (I2C) Interface ............................................................................ 296
14.1
Block Diagram ................................................................................................................................... 296
14.2
Functional Description ....................................................................................................................... 296
14.2.1 I2C Bus Functional Overview ............................................................................................................. 297
14.2.2 Available Speed Modes ..................................................................................................................... 304
14.3
Initialization and Configuration........................................................................................................... 305
14.4
Register Map ..................................................................................................................................... 306
14.5
Register Descriptions (I2C Master).................................................................................................... 306
14.6
Register Descriptions (I2C Slave)...................................................................................................... 320


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