LM3S315 Data Sheet
October 8, 2006
5
Preliminary
10.
Watchdog Timer ................................................................................................................ 176
10.1
Block Diagram ................................................................................................................................... 176
10.2
Functional Description ....................................................................................................................... 177
10.3
Initialization and Configuration........................................................................................................... 177
10.4
Register Map ..................................................................................................................................... 177
10.5
Register Descriptions......................................................................................................................... 178
11.
Analog-to-Digital Converter (ADC) .................................................................................. 199
11.1
Block Diagram ................................................................................................................................... 200
11.2
Functional Description ....................................................................................................................... 200
11.2.1 Sample Sequencers .......................................................................................................................... 200
11.2.2 Module Control .................................................................................................................................. 201
11.2.3 Hardware Sample Averaging Circuit.................................................................................................. 202
11.2.4 Analog-to-Digital Converter ............................................................................................................... 202
11.2.5 Test Modes ........................................................................................................................................ 202
11.2.6 Internal Temperature Sensor ............................................................................................................. 202
11.3
Initialization and Configuration........................................................................................................... 202
11.3.1 Module Initialization ........................................................................................................................... 203
11.3.2 Sample Sequencer Configuration ...................................................................................................... 203
11.4
Register Map ..................................................................................................................................... 203
11.5
Register Descriptions......................................................................................................................... 204
12.
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 229
12.1
Block Diagram ................................................................................................................................... 230
12.2
Functional Description ....................................................................................................................... 230
12.2.1 Transmit/Receive Logic ..................................................................................................................... 230
12.2.2 Baud-Rate Generation ....................................................................................................................... 231
12.2.3 Data Transmission ............................................................................................................................. 232
12.2.4 FIFO Operation .................................................................................................................................. 232
12.2.5 Interrupts............................................................................................................................................ 232
12.2.6 Loopback Operation .......................................................................................................................... 233
12.3
Initialization and Configuration........................................................................................................... 233
12.4
Register Map ..................................................................................................................................... 234
12.5
Register Descriptions......................................................................................................................... 235
13.
Synchronous Serial Interface (SSI) ................................................................................. 265
13.1
Block Diagram ................................................................................................................................... 265
13.2
Functional Description ....................................................................................................................... 266
13.2.1 Bit Rate Generation ........................................................................................................................... 266
13.2.2 FIFO Operation .................................................................................................................................. 266
13.2.3 Interrupts............................................................................................................................................ 266
13.2.4 Frame Formats .................................................................................................................................. 267
13.3
Initialization and Configuration........................................................................................................... 274
13.4
Register Map ..................................................................................................................................... 275
13.5
Register Descriptions......................................................................................................................... 276
14.
Analog Comparator........................................................................................................... 300
14.1
Block Diagram ................................................................................................................................... 300
14.2
Functional Description ....................................................................................................................... 300
14.2.1 Internal Reference Programming....................................................................................................... 301
14.3
Initialization and Configuration........................................................................................................... 302
14.4
Register Map ..................................................................................................................................... 303
14.5
Register Descriptions......................................................................................................................... 303