LM3S316 Data Sheet
October 8, 2006
3
Preliminary
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 18
About This Document..................................................................................................................... 19
Audience ........................................................................................................................................................... 19
About This Manual............................................................................................................................................ 19
Related Documents .......................................................................................................................................... 19
Documentation Conventions............................................................................................................................. 19
1.
Architectural Overview ....................................................................................................... 22
1.1
Product Features ................................................................................................................................. 22
1.2
Target Applications .............................................................................................................................. 26
1.3
High-Level Block Diagram ................................................................................................................... 27
1.4
Functional Overview ............................................................................................................................ 28
1.4.1
ARM Cortex™-M3 ............................................................................................................................... 28
1.4.2
Motor Control Peripherals .................................................................................................................... 28
1.4.3
Analog Peripherals .............................................................................................................................. 29
1.4.4
Serial Communications Peripherals..................................................................................................... 29
1.4.5
System Peripherals.............................................................................................................................. 30
1.4.6
Memory Peripherals............................................................................................................................. 31
1.4.7
Additional Features .............................................................................................................................. 32
1.4.8
Hardware Details ................................................................................................................................. 32
1.5
System Block Diagram ........................................................................................................................ 33
2.
ARM Cortex-M3 Processor Core........................................................................................ 34
2.1
Block Diagram ..................................................................................................................................... 35
2.2
Functional Description ......................................................................................................................... 35
2.2.1
Serial Wire and JTAG Debug .............................................................................................................. 35
2.2.2
Embedded Trace Macrocell (ETM) ...................................................................................................... 36
2.2.3
Trace Port Interface Unit (TPIU) .......................................................................................................... 36
2.2.4
ROM Table .......................................................................................................................................... 36
2.2.5
Memory Protection Unit (MPU) ............................................................................................................ 36
2.2.6
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36
3.
Memory Map ........................................................................................................................ 37
4.
Interrupts ............................................................................................................................. 39
5.
JTAG Interface .................................................................................................................... 42
5.1
Block Diagram ..................................................................................................................................... 43
5.2
Functional Description ......................................................................................................................... 43
5.2.1
JTAG Interface Pins............................................................................................................................. 44
5.2.2
JTAG TAP Controller ........................................................................................................................... 45
5.2.3
Shift Registers ..................................................................................................................................... 46
5.2.4
Operational Considerations ................................................................................................................. 46
5.3
Initialization and Configuration............................................................................................................. 47
5.4
Register Descriptions........................................................................................................................... 48
5.4.1
Instruction Register (IR) ....................................................................................................................... 48
5.4.2
Data Registers ..................................................................................................................................... 50
6.
System Control.................................................................................................................... 52
6.1
Functional Description ......................................................................................................................... 52
6.1.1
Device Identification............................................................................................................................. 52