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XC167-16 Datasheet(PDF) 75 Page - Infineon Technologies AG |
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XC167-16 Datasheet(HTML) 75 Page - Infineon Technologies AG |
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75 / 442 page  XC167-16 Derivatives Peripheral Units (Vol. 2 of 2) Real Time Clock User’s Manual 15-5 V2.0, 2004-04 RTC_X8, V2.1 15.2 RTC Run Control If the RTC shall operate bit RUN in register RTC_CON must be set (default after reset). Bit RUN can be cleared, for example, to exclude certain operation phases from time keeping. The RTC can be completely disabled by setting the corresponding bit RTCDIS in register SYSCON3. Note: A valid count clock is required for proper RTC operation, of course. A reset for the RTC is triggered via software by setting bit RTCRST in register SYSCON0. In this case all RTC registers are set to their initial values and bit RTCRST is cleared automatically. A normal system reset does not affect the RTC registers and its operation (RTC_IC will be reset, however). The initialization software must ensure the proper RTC operating mode. The RTC control register RTC_CON selects the basic operation of the RTC module. RTC_CON Control Register ESFR (F110 H/88H) Reset Value: 8003 H 15 14 13 12 11 10 9876543 210 ACC POS ------ ---- REF CLK T14 INC T14 DEC PRE RUN rh ------ ---- rw rwh rwh rw rw Field Bits Type Description ACCPOS 15 rh RTC Register Access Possible 0 No write access is possible, only asynchronous reads 1 Registers can be read and written REFCLK 4rw Reference Clock Source 0 The RTC count clock is derived from the auxiliary oscillator ( f OSCa) 1 The RTC count clock is derived from the main oscillator ( f OSCm/32) T14INC 3rwh Increment Timer T14 Value Setting this bit to 1 adds one count pulse upon the next count event, thus incrementing T14. This bit is cleared by hardware after incrementation. T14DEC 2rwh Decrement Timer T14 Value Setting this bit to 1 suppresses the next count event, thus decrementing T14. This bit is cleared by hardware after decrementation. |
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