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ATXMEGA128A4-AU Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATXMEGA128A4-AU Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 74 page  10 8069D–AVR–08/08 XMEGA A4 7.4 Data Memory The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin- ear address space, see Figure 7-2 on page 10. To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices. 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc- tions on these registers. The I/O memory address for all peripherals and modules in XMEGA A4 is shown in the ”Periph- eral Module Address Map” on page 51. Figure 7-2. Data Memory Map (Hexadecimal address) Byte Address ATxmega64A4 Byte Address ATxmega32A4 Byte Address ATxmega16A4 0 I/O Registers (4KB) 0 I/O Registers (4KB) 0 I/O Registers (4KB) FFF FFF FFF 1000 EEPROM (2K) 1000 EEPROM (2K) 1000 EEPROM (1K) 17FF 17FF 17FF RESERVED RESERVED RESERVED 2000 Internal SRAM (4K) 2000 Internal SRAM (4K) 2000 Internal SRAM (2K) 2FFF 2FFF 27FF 3000 External Memory (0 to 16 MB) 3000 External Memory (0 to 16 MB) 2800 External Memory (0 to 16 MB) FFFFFF FFFFFF FFFFFF Byte Address ATxmega128A4 0 I/O Registers (4KB) FFF 1000 EEPROM (2K) 17FF RESERVED 2000 Internal SRAM (8K) 3FFF 4000 External Memory (0 to 16 MB) FFFFFF |
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