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DR80390 Datasheet(PDF) 7 Page - Digital Core Design |
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DR80390 Datasheet(HTML) 7 Page - Digital Core Design |
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7 / 84 page  DR80390 Instructions set details - 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 1. OVERVIEW 1.1. DOCUMENT STRUCTURE. Document contains brief description of DR80390 instructions. This manual is intended for design engineers who are planning to use the DR80390 HDL core in conjunction with software assembler, compiler and debugger tools. 2. INSTRUCTIONS SET BRIEF Some instruction opcodes of DR80390 are different in FLAT and LARGE modes. The details are described in this chapter. 2.1. INSTRUCTION SET NOTES The DR80390 has five different addressing modes: immediate, direct, register, indirect and relative. In the immediate addressing mode the data is contained in the opcode. By direct addressing an eight bit address is a part of the opcode, by register addressing, a register is selected in the opcode for the operation. In the indirect addressing mode, a register is selected in the opcode to point to the address used by the operation. The relative addressing mode is used for jump instructions. The following tables give a survey about the instruction set cycles of the DR80390 microcontroller core. One cycle is equal to one clock period. First two tables contain notes for mnemonics used in Instruction set tables. The next tables show instruction hexadecimal codes, number of bytes and machine cycles that each instruction takes to execute. Rn Working register R0-R7 direct 128 internal RAM locations, any Special Function Registers @Ri Indirect internal or external RAM location addressed by register R0 or R1 #data 8-bit constant included in instruction #data16 16-bit constant included as bytes 2 and 3 of instruction #data24 24-bit constant included as bytes 2,3 and 4 of instruction bit 256 software flags, any bit-addressable l/O pin, control or status bit A Accumulator Table 1. Notes on data addressing modes addr24 Destination address for LCALL and LJMP may be anywhere within the 16 MB of program memory address space in FLAT mode. addr19 Destination address for ACALL and AJMP will be within the same 512 KB page of program memory as the first byte of the following instruction in FLAT mode addr16 Destination address for LCALL and LJMP may be anywhere within the 64 kB of program memory address space in LARGE mode. addr11 Destination address for ACALL and AJMP will be within the same 2 KB page of program memory as the first byte of the following instruction in LARGE mode rel SJMP and all conditional jumps include an 8-bit offset byte. Range is +127/-128 bytes relative to the first byte of the following instruction Table 2. Notes on program addressing modes |
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