ADXL180 datasheet(50/56 Pages) AD

Part #	ADXL180

Description	Configurable, High g, iMEMS Accelerometer

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ADXL180

Rev. 0 | Page 50 of 56

CONFIGURATION REGISTER REFERENCE

The following tables define the codes for each programmable field in the three configuration registers (CREG0, CREG1, and CREG2).

The default setting (unprogrammed state) of all bits in all configuration registers is zero. As a result, the default configuration of the

ADXL180 is compatible with the ADIFX operation mode and communication protocol as implemented in the ADXS101 satellite

transmitter.

Table 44. Configuration and User Data Bit Map

Configuration

Mode Register

Address

Configuration

Mode Register

Name

MSB

D6

D5

D4

D3

D2

D1

LSB

D7

D0

0000b

UREG

UD7

UD6

UD5

UD4

UD3

UD2

UD1

UD0

0001b

CREG0

UD8

BDE

MD1

MD0

FDLY

DLY2

DLY1

DLY0

0010b

CREG1

STI

AZE

SYEN

ADME

ERC

SVD

DAT

MAN

0011b

CREG2

CUPRG

CUPAR

SCOE

FC1

FC0

RG2

RG1

RG0

0100b…1001b

NU

X

1010b

CMEXIT

1

0

1011b

SN0

SNB7

SNB6

SNB5

SNB4

SNB3

SNB2

SNB1

SNB0

1100b

SN1

SNB15

SNB14

SNB13

SNB12

SNB11

SNB10

SNB9

SNB8

1101b

SN2

SNB23

SNB22

SNB21

SNB20

SNB19

SNB18

SNB17

SNB16

1110b

SN3

SNB31

SNB30

SNB29

SNB28

SNB27

SNB26

SNB25

SNB24

1111b

MFGID

SNPRG

SNPAR

REV2

REV1

REV0

MFGID2

MFGID1

MFGID0

1 X = don’t care.

2 NU = not used.

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