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AD2S1210CSTZ Datasheet(PDF) 6 Page - Analog Devices |
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AD2S1210CSTZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 36 page AD2S1210 Rev. 0 | Page 6 of 36 TIMING SPECIFICATIONS AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.1 Table 2. Parameter Description Limit at TMIN, TMAX Unit fCLKIN Frequency of clock input 6.144 MHz min 10.24 MHz max tCK Clock period ( = 1/fCLKIN) 98 ns min 163 ns max t1 A0 and A1 setup time before RD/CS low 2 ns min t2 Delay CS falling edge to WR/FSYNC rising edge 22 ns min t3 Address/data setup time during a write cycle 3 ns min t4 Address/data hold time during a write cycle 2 ns min t5 Delay WR/FSYNC rising edge to CS rising edge 2 ns min t6 Delay CS rising edge to CS falling edge 10 ns min t7 Delay between writing address and writing data 2 × tCK + 20 ns min t8 A0 and A1 hold time after WR/FSYNC rising edge 2 ns min t9 Delay between successive write cycles 6 × tCK + 20 ns min t10 Delay between rising edge of WR/FSYNC and falling edge of RD 2 ns min t11 Delay CS falling edge to RD falling edge 2 ns min t12 Enable delay RD low to data valid in configuration mode VDRIVE = 4.5 V to 5.25 V 37 ns min VDRIVE = 2.7 V to 3.6 V 25 ns min VDRIVE = 2.3 V to 2.7 V 30 ns min t13 RD rising edge to CS rising edge 2 ns min t14A Disable delay RD high to data high-Z 16 ns min t14B Disable delay CS high to data high-Z 16 ns min t15 Delay between rising edge of RD and falling edge of WR/FSYNC 2 ns min t16 SAMPLE pulse width 2 × tCK + 20 ns min t17 Delay from SAMPLE before RD/CS low 6 × tCK + 20 ns min t18 Hold time RD before RD low 2 ns min t19 Enable delay RD/CS low to data valid VDRIVE = 4.5 V to 5.25 V 17 ns min VDRIVE = 2.7 V to 3.6 V 21 ns min VDRIVE = 2.3 V to 2.7 V 33 ns min t20 RD pulse width 6 ns min t21 A0 and A1 set time to data valid when RD/CS low VDRIVE = 4.5 V to 5.25 V 36 ns min VDRIVE = 2.7 V to 3.6 V 37 ns min VDRIVE = 2.3 V to 2.7 V 29 ns min t22 Delay WR/FSYNC falling edge to SCLK rising edge 3 ns min t23 Delay WR/FSYNC falling edge to SDO release from high-Z VDRIVE = 4.5 V to 5.25 V 16 ns min VDRIVE = 2.7 V to 3.6 V 26 ns min VDRIVE = 2.3 V to 2.7 V 29 ns min t24 Delay SCLK rising edge to DBx valid VDRIVE = 4.5 V to 5.25 V 24 ns min VDRIVE = 2.7 V to 3.6 V 18 ns min VDRIVE = 2.3 V to 2.7 V 32 ns min t25 SCLK high time 0.4 × tCK ns min t26 SCLK low time 0.4 × tCK ns min t27 SDI setup time prior to SCLK falling edge 3 ns min t28 SDI hold time after SCLK falling edge 2 ns min |
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