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AD1883 Datasheet(PDF) 6 Page - Analog Devices |
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AD1883 Datasheet(HTML) 6 Page - Analog Devices |
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Rev. 0 | Page 6 of 20 | April 2008 AD1883 MICROPHONE BIAS MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = 5 V or 3.3 V VREF Setting = High-Z High-Z VREF Setting = 0 V 0 V dc VREF Setting = 50% 1.65 V dc MIC_BIAS_IN (Pin 33) = 5 V VREF Setting = 80% 3.7 V dc VREF Setting = 100% 3.9 V dc MIC_BIAS_IN (Pin 33) = 3.3 V VREF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc MIC_BIAS-E (When Enabled as BIAS) VREF Setting = High-Z High-Z VREF Setting = 0 V 0 V dc VREF Setting = 50% 1.65 V dc VREF Setting = 80% 2.86 V dc VREF Setting = 100% 3.0 V dc Output Drive Current VREF Setting = 50%, 80%, or 100% 1.6 mA GPIO 0 Input Signal High (VIH)DVIO × 0.60 DVIO V Input Signal Low (VIL)0 DVIO × 0.24 V Output Signal High (VOH) IOUT = –500 μADVIO × 0.72 DVIO V Output Signal Low (VOL)IOUT = +1500 μA0 DVIO × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)–50 μA GPIO 1 and GPIO 2 Input Signal High (VIH)AVDD × 0.60 AVDD V Input Signal Low (VIL)0 AVDD × 0.24 V Output Signal High (VOH)IOUT = –500 μAAVDD × 0.72 AVDD V Output Signal Low (VOL)IOUT = +1500 μA0 AVDD × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)–50 μA DM Clock Output Signal High (VOH)IOUT = –500 μAAVDD × 0.72 AVDD V Output Signal Low (VOL)IOUT = +1500 μA0 AVDD × 0.10 V DM_1/2 and DM_2 Input Signal High (VIH)AVDD × 0.60 AVDD V Input Signal Low (VIL)0 AVDD × 0.24 V Input Leakage Current (Signal High) (IIH) –150 nA Input Leakage Current (Signal Low) (IIL)–50 nA S/PDIF_Out Input Signal High (VIH)DVIO × 0.60 DVIO V Input Signal Low (VIL)0 DVIO × 0.24 V Output Signal High (VOH) IOUT = –500 μADVIO × 0.72 DVIO V Output Signal Low (VOL)IOUT = +1500 μA0 DVIO × 0.10 V Input Leakage Current (Signal High) (IIH) 150 nA Input Leakage Current (Signal Low) (IIL)–50 μA Parameter Min Typ Max Unit |
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