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SN74AUP2G126YZPR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP2G126YZPR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 16 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) SN74AUP2G126 LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES687B – JANUARY 2007 – REVISED JANUARY 2008 The SN74AUP2G126 is a dual bus driver/line driver with 3-state outputs, designed for 0.8-V to 3.6-V VCC operation. The outputs are disabled when the associated output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YFP Reel of 3000 SN74AUP2G126YFPR _ _ _ HN_ (Pb-free) NanoFree™ – WCSP (DSBGA) –40 °C to 85°C 0.23-mm Large Bump – YZP Reel of 3000 SN74AUP2G126YZPR _ _ _ HN_ (Pb-free) QFN – RSE Reel of 3000 SN74AUP2G126RSER HN VSSOP – DCU Reel of 3000 SN74AUP2G126DCUR H26_ (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (3) YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). DCU: The actual top-side marking has one additional character to designate the assembly/test site. FUNCTION TABLE INPUTS OUTPUT Y OE A H H H H L L L X(1) Z (1) Floating inputs allowed 2 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): SN74AUP2G126 |
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