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VS(FrameValid)

HS(LineValid)

A

B

C

B

D

E

LastVisibleLine

A - TimebetweenVSandHSrisingedge:

B-Numberofpixelinactiveline:

C-Horizonallineblanking:

D- TimebetweenVSandHSfallingedge:

E- TimebetweenHSfallingandHSrisingedge:

0

t

0

t

8x1/f

t

0

t

ifMODE=highort =0:8x1/f

t

£

£

£

£

B

DCLK

C

D

D

DCLK

E

ifMODE=lowort >0:12x1/f

t

D

DCLK

E

£

MIPI CSI-1 / CCP2-Class 0 Interface

CLK+

D0+/-

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

0

0

0

1

1

1

0

0

0

0

0

0

0

1

SN65LVDS315

SLLS881A – DECEMBER 2007 – REVISED MARCH 2008

The relationship between frame sync and line sync shall be the following:

Figure 2. VS and HS Timing Diagram

When MODE is held low, the SN65LVDS315 provides a MIPI CSI-1 compliant serial output. The output data on

DOUT is set on each falling edge of the differential clock signal, CLK. The CSI-1/CCP2 receiver should latch the

data in on the rising CLK edge. The clock signal is free running (and not gated as optional in the CCP2 spec).

The data format is bytewise (8-bit boundary) with the least significant bit (LSB) sent first. When nothing is being

transferred (e.g. during blanking), DOUT remains high, except during power shutdown.

Figure 3. Data and Clock Output in CSI-1/CCP2

Camera Mode Class-0 Transferring a Data Sequence of 0xFF011223h

Copyright © 2007–2008, Texas Instruments Incorporated

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