BASIC INTEGRATION CYCLE

0.75pF

0.75pF

VREF

ToConverter

S

RESET

S

REF

S

ADC1A

S

INTA

S

REF

S

INTB

IN1

ESD

Protection

Diodes

Input

Current

IntegratorA

IntegratorB(sameasA)

Photodiode

1.5pF

Range[1]

Range[0]

S

ADC1A

VREF

IntegratorA

VoltageOutput

Configurationof

IntegratorA

Wait

Convert

Wait

Convert

Integrate

S

REF

S

INTA

S

INTB

S

RESET

CONV

CLK

IntegrateonSideB

IntegrateonSideA

IntegrateonSideB

DDC316

The topology of the front-end of the DDC316 is an

The timing relationships of all of the switches shown

analog integrator, as shown in Figure 5. In this

in Figure 5 are illustrated in Figure 6. Note that

diagram, only input IN1 is shown. The input stage

Figure

6

conceptualizes

the

operation

of

the

consists of an operational amplifier, a selectable

integrator input stage of the DDC316 and should not

feedback

capacitor

network

and

several

be used as an exact timing tool for design.

switches that implement the integration cycle.

Figure 5. Basic Integration Configuration for Input 1

Figure 6. Conceptual Basic Integration Timing Diagram of Integrator A (as Illustrated in Figure 5)

10

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