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ADS7883SBDBVR Datasheet(PDF) 10 Page - Texas Instruments |
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ADS7883SBDBVR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 17 page Invalid Data Valid Data SDO 1 5 4 3 2 6 10 9 8 7 13 12 11 16 15 14 1 5 4 3 2 6 10 9 8 7 13 12 11 16 15 14 SCLK Device Fully Powered-Up Device Starts Powering Up CS ADS7883 SLAS594 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For the device to reach the fully powered up condition requires 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 23. Note that the power-up time of 0.8 µs is more than a single conversion cycle at 3-MSPS speed. This means the device requires three dummy conversion frames at 3-MSPS speed or one elongated dummy conversion frame. The data during the dummy conversion frames is invalid. Figure 23. Exiting Power-Down Mode 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7883 |
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