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BQ24152 Datasheet(PDF) 25 Page - Texas Instruments

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Part No. BQ24152
Description  Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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BQ24152 Datasheet(HTML) 25 Page - Texas Instruments

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bq24152 I2C Update Sequence
S
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
A/A
P
Data Transferred
‘0’ (Write)
(n Bytes+ Acknowledge)
Frommasterto bq24152
A
= Acknowledge(SDA LOW)
A
= Notacknowledge(SDA
HIGH)
From bq24152tomaster
S
=STARTcondition
Sr
=RepeatedSTARTcondition
P
=STOP condition
(a) F/S-Mode
F/S-Mode
HS-Mode
S
HS-MASTERCODE
A
Sr
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
A/A
P
Data Transferred
‘0’ (write)
(n Bytes+ Acknowledge)
Sr
Slave A.
(b)HS- Mode
F/S-Mode
HS-Mode
Continues
Slave Address Byte
bq24152
www.ti.com ...................................................................................................................................................................................................... SLUS847 – JUNE 2008
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of
the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from remaining in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
The bq24152 requires a start condition, a valid I2C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, bq24152 device acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I2C address selects the bq24152. The bq24152 performs an update on the
falling edge of the acknowledge signal that follows the LSB byte.
For the first update, bq24152 requires a start condition, a valid I2C address, a register address byte, a data byte.
For all consecutive updates, bq24152 needs a register address byte, and a data byte. Once a stop condition is
received, the bq24152 releases the I2C bus, and awaits a new start conditions.
Figure 31. Data Transfer Format in F/S Mode and H/S Mode
MSB
LSB
X
1
1
0
1
0
1
1
Copyright © 2008, Texas Instruments Incorporated
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