SERIAL INTERFACE DESCRIPTION

F/S Mode Protocol

STARTCondition

DATA

CLK

STOP Condition

S

P

DATA

CLK

DataLine

Stable;

DataValid

Change

ofData

Allowed

bq24152

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The bq24152 device works as a slave and supports the following data transfer modes, as defined in the

in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

intact as long as supply voltage remains above 2.2 V (typical).

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to

as the HS-mode. The bq24152 device only supports 7-bit addressing. The device 7-bit address is defined as

‘1101011’ (6BH).

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

recognize a start condition.

Figure 27. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 28). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

Figure 28. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

Copyright © 2008, Texas Instruments Incorporated

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