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ADS7866 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS7866 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 17 page NORMAL OPERATION 1 2 3 11 12 14 15 CS SCLK SDO 0 0 D11 D10 D2 D1 D0 13 0 0 16 td1 td2 th1 tconv tq td3 b tsu1 a td4 tacq a t w1 POWER-DOWN MODE 1 2 3 4 5 9 10 16 CS SCLK SDO td5 td6 ADS7883 www.ti.com ....................................................................................................................................................................................................... SLAS594 – JULY 2008 The cycle begins with the falling edge of CS. This point is indicated as a in Figure 21. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains two leading zeros, followed by 12-bit data in MSB first format and padded by two lagging zeros. The falling edge of CS clocks out the first zero, and a second zero is clocked out on the first falling edge of the clock. Data is in MSB first format with the MSB being clocked out on the 2nd falling edge. Data is padded with two lagging zeros as shown in Figure 21. The conversion ends on the first rising edge of SCLK after the 13th falling edge. At this point the device enters the acquisition phase. This point is indicated by b in Figure 21. Figure 21 shows the device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any time after point b. SDO goes to 3-state with the CS high level. The next conversion should not be started (by pulling CS low) until the end of the quiet sampling time (tq) after SDO goes to 3-state or until the minimum acquisition time (tacq) has elapsed. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle. (Also refer to the Power-Down Mode section for more details.) CS going high any time during the conversion aborts the ongoing conversion and SDO goes to 3-state. The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are received from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in the Electrical Specifications table. Figure 21. Interface Timing Diagram The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. An ongoing conversion stops and SDO goes to 3-state under this power-down condition as shown in Figure 22. Figure 22. Entering Power-Down Mode Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS7883 |
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