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ADS7883 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS7883 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 17 page DEVICE INFORMATION 3 2 4 6 1 VDD GND VIN CS SCLK SDO 5 ADS7883 www.ti.com ....................................................................................................................................................................................................... SLAS594 – JULY 2008 TIMING REQUIREMENTS (see Figure 21) (continued) All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified. PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT VDD = 2.7 V to 4.5 V 32 Frequency, SCLK MHz VDD = 4.5 V to 5.5 V 48 Delay time, second falling edge of clock and CS to VDD = 3 V –2 4 td5 enter in powerdown (use min spec not to accidently ns VDD = 5 V –2 3 enter in powerdown) see Figure 22 Delay time, CS and 10th falling edge of clock to enter VDD = 3 V –2 4 td6 in powerdown (use max spec not to accidently enter ns VDD = 5 V –2 3 in powerdown) see Figure 22 SOT23 PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. VDD 1 – Power supply input, also acts like a reference voltage to ADC. GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin. VIN 3 I Analog signal input SCLK 4 I Serial clock SDO 5 O Serial data out CS 6 I Chip select signal, active low Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS7883 |
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