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EMC326SP16AKZ-12L Datasheet(PDF) 5 Page - Emerging Memory & Logic Solutions Inc |
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EMC326SP16AKZ-12L Datasheet(HTML) 5 Page - Emerging Memory & Logic Solutions Inc |
5 / 52 page EMC326SP16AK 2Mx16 CellularRAM AD-MUX 5 Preliminary List of Tables Table 1: Signal Descriptions ........................................................................................................................................... 7 Table 2: Bus Operations ................................................................................................................................................. 8 Table 3: Sequence and Burst Length .............................................................................................................................. 24 Table 4: Drive Strength ................................................................................................................................................... 25 Table 5: Variable Latency Configuration Codes............................................................................................................... 26 Table 6: Fixed Latency Configuration Codes................................................................................................................... 27 Table 7: Address Patterns for PAR(RCR[4] =1)............................................................................................................... 29 Table 8: Device Identification Register Mapping ............................................................................................................. 29 Table 9: Absolute Maximum Ratings ............................................................................................................................... 30 Table 10: Electrical Characteristics and Operating Conditions ......................................................................................... 30 Table 11: Capacitance ...................................................................................................................................................... 31 Table 12: Asynchronous READ Cycle Timing Requirements ............................................................................................ 32 Table 13: Burst READ Cycle Timing Requirements ......................................................................................................... 33 Table 14: Asynchronous WRITE Cycle Timing Requirements .......................................................................................... 34 Table 15: Burst WRITE Cycle Timing Requirements ......................................................................................................... 35 Table 16: Initialization Timing Parameters ........................................................................................................................ 36 |
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