EMC326SP16AK

2Mx16 CellularRAM AD-MUX

8

Preliminary

Table 2: BUS OPERATIONS

Note:

1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power

during standby mode.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is

in the select mode, DQ[15:8] are enabled.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.

6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.

7. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated

by WAIT).

Asynchfonous Mode

BCR[15]=1

Power

CLK ADV#

CE#

OE#

WE#

CRE

UB#/

LB#

DQ[15:0]

Notes

Read

Active

X

L

L

H

L

L

Low-z

Data out

4

Write

Active

X

L

X

L

L

L

High-z

Data in

4

Standby

Standby

H or L

X

H

X

X

L

X

High-z

High-z

5, 6

No operation

Idle

X

X

L

X

X

L

X

Low-z

X

4, 6

Configuration register

write

Active

X

L

H

L

H

X

Low-z

High-z

Configuration register

read

Active

X

L

L

H

H

L

Low-z

Config.

Reg.out

Burst Mode

BCR[15]=0

Power

CLK ADV#

CE#

OE#

WE#

CRE

UB#/

LB#

WAIT

DQ[15:0]

Notes

Async read

Active

H or L

L

L

H

L

L

Low-z

Data out

4, 7

Async write

Active

H or L

L

X

L

L

L

Low-z

Data in

4

Standby

Standby

H or L

X

H

X

X

L

X

High-z

High-z

5, 6

No operation

Idle

H or L

X

L

X

X

L

X

Low-z

X

4, 6

Initial burst read

Active

L

L

X

H

L

L

Low-z

Address

4, 8

Initial burst write

Active

L

L

H

L

L

X

Low-z

Address

4, 8

Burst continue

Active

H

L

X

X

X

L

Low-z

Data out

or

Data in

4, 8

Configuration register

write

Active

L

L

H

L

H

X

Low-z

High-z

8, 9

Configuration register

read

Active

L

L

L

H

H

L

Low-z

Config.

Reg.out

8, 9