EMC326SP16AK

2Mx16 CellularRAM AD-MUX

7

Preliminary

Table 1: SIGNAL DESCRIPTIONS

Note:

1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.

Symbol

Type

Descriptions

A[20:16]

Input

Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally

latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded

into the BCR or the RCR.

CLK

(note1)

Input

Clock: Synchronizes the memory to the system operating frequency during synchronous operations.

When configured for synchronous operation, the address is latched on the first rising CLK edge when

ADV# is active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE

operations when burst mode is enabled.

ADV#

(note1)

Input

Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on

the rising edge of ADV# during asynchronous READ and WRITE operations.

CRE

Input

Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ

operations access the RCR, BCR, or DIDR.

CE#

Input

Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into

standby mode.

OE#

Input

Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are

disabled.

WE#

Input

Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either

a configuration register or to the memory array.

LB#

Input

Lower byte enable. DQ[7:0]

UB#

Input

Upper byte enable. DQ[15:8]

A/DQ[15:0] Input/Output

Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins

behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address,

RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH.

WAIT

(note1)

Output

Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate

collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless

wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z

when CE# is HIGH.

RFU

-

Reserved for future use.

VCC

Supply

Device power supply: (1.70V.1.95V) Power supply for device core operation.

VCCQ

Supply

I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.

VSS

Supply

VSS must be connected to ground.

VSSQ

Supply

VSSQ must be connected to ground.