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PSD835F3V-C-20U Datasheet(PDF) 7 Page - STMicroelectronics |
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PSD835F3V-C-20U Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 110 page PSD8XX Architectural Overview (cont.) 4.5 ISP via JTAG Port In-System Programming can be performed through the JTAG pins on Port E. This serial interface allows complete programming of the entire PSD835G2 device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin assignments. 4.6 In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD835G2 (memory, logic, configuration) device can be programmed or erased without the use of the microcontroller. Port E Pins JTAG Signal PE0 TMS PE1 TCK PE2 TDI PE3 TDO PE4 TSTAT PE5 TERR Table 3. JTAG Signals on Port E PSD8XX Family PSD835G2 6 4.7 In-Application re-Programming (IAP) The main Flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the secondary Flash memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary Flash boot memory can be programmed the same way by executing out of the main Flash memory. Table 4 indicates which programming methods can program different functional blocks of the PSD8XX. Device Functional Block JTAG-ISP Programmer IAP Main Flash memory Yes Yes Yes Flash Boot memory Yes Yes Yes PLD Array (DPLD and CPLD) Yes Yes No PSD Configuration Yes Yes No Table 4. Methods of Programming Different Functional Blocks of the PSD835G2 4.8 Page Register The eight-bit Page Register expands the address range of the microcontroller by up to 256 times.The paged address can be used as part of the address space to access external memory and peripherals or internal memory and I/O. The Page Register can also be used to change the address mapping of blocks of Flash memory into different memory spaces for IAP. 4.9 Power Management Unit The Power Management Unit (PMU) in the PSD835G2 gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD835G2 also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and the CPLD will latch its outputs and go to standby until the next transition on its inputs. Additionally, bits in the PMMR2 register can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See section 9.5. |
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