97SD3248 datasheet(10/40 Pages) MAXWELL

Part #	97SD3248

Description	1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

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Manufacturer	MAXWELL [Maxwell Technologies]

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97SD3248

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All data sheets are subject to change without notice

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM

05.10.06 Rev 4

DQM Truth Table

Note: H: V

IH L: VIL x VIH or VIL

Write: I

DID is Needed

Read: I

DOD is Needed

The SDRAM can mask input/output data by means of DQM.

During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other

hand, when DQM is set High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held

( the new data is not written). Desired data can be masked during burst read or burst write by setting DQM..

For more details, refer to the DQM control section of the SDRAM operating instructions.

CKE Truth Table

Note: H:V

IH L:VIL x VIH or VIL

COMMAND

SYMBOL

CKE = N-1

CKE = N

DQM

Byte (DQ0 to DQ47) write enable/output

enable

ENB

H

x

L

Byte (DQ0 to DQ47) write inhibit/output dis-

able

MASK

H

x

H

CURRENT STATE

COMMAND

N

-1

N

CS

RAS

CAS

WE

ADDRESS

Active

Clock suspended mode entry

H

L

x

Any

Clock Suspend

L

x

Clock Suspend

Clock Suspend mode exit

L

H

x

Idle

Auto-refresh command (REF)

H

L

H

x

Idle

Self-refresh entry (SELF)

H

L

H

x

Idle

Power down entry

HL

LH

H

x

H

L

HL

xxx

x

Self Refresh

Self Refresh exit (SELFX)

L

H

L

H

x

Power down

Power down exit

LH

H

x

L

H

xxx

x

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